// (C) 2022 Intel Corporation. All rights reserved.
// Your use of Intel Corporation's design tools, logic functions and other 
// software and tools, and its AMPP partner logic functions, and any output 
// files from any of the foregoing (including device programming or simulation 
// files), and any associated documentation or information are expressly subject 
// to the terms and conditions of the Intel Program License Subscription 
// Agreement, Intel FPGA IP License Agreement, or other applicable 
// license agreement, including, without limitation, that your use is for the 
// sole purpose of programming logic devices manufactured by Intel and sold by 
// Intel or its authorized distributors.  Please refer to the applicable 
// agreement for further details

module postcode_fub
  (
   // ------------------------
   // Clock and Reset signals
   // ------------------------
   input                    iClk,                                        //clock for sequential logic 
   input                    iRst_n,                                      //reset signal from PLL Lock, resets state machine to initial state
   // ----------------------------
   // inputs and outputs
   // ----------------------------
   //Master 
   input [3:0]              iMASTER_POST_CODE,                           //Master Sequence State post-code, from CPU FPGA thru sGPIO
   //SCM_AUX
   input                    iSCM_BMC_AUX_PWR_FAULT,                      //SCM side AUX power fault info, from CPU FPGA thru sGPIO
   input                    iSCM_PWR_FAULT,
   input                    iBMC_PWR_FAULT,
   //CPU_AUX
   input                    iCPU_AUX_PWR_FLT,                            //no actual CPU_AUX power error code
   //PSU_MAIN
   input                    iP5V_MAIN_PWR_FAULT,                         //SCM side main power fault info, from CPU FPGA thru sGPIO
   input [2:0]        	    iPSU_FLT_CODE,                               //MB PSU FLT CODE, from CPU FPGA thru sGPIO
   //CPU_MAIN
   input [7:0]              iCPU0_FLT_CODE,                              //CPU0 MAIN POWER FLT CODE, from CPU FPGA thru sGPIO
   input [7:0]              iCPU1_FLT_CODE,                              //CPU1 MAIN POWER FLT CODE, from CPU FPGA thru sGPIO
   //MEM
   input [5:0]              iCPU0_DIMM_FLT_CODE,                         //DIMM FLT CODE, from CPU FPGA thru sGPIO
   input [5:0]              iCPU1_DIMM_FLT_CODE,                         //DIMM FLT CODE, from CPU FPGA thru sGPIO	
   
   output reg [7:0]         oDisplay1,
   output reg [7:0]         oDisplay2
   
   );
   
   //////////////////////////////////////////////////////////////////////////////////
    // States for FSM
   //////////////////////////////////////////////////////////////////////////////////
   localparam ST_INIT               = 4'd0;
   localparam ST_SCM_AUX            = 4'd1;
   localparam ST_CPU_AUX	         = 4'd2;
   localparam ST_PSU_MAIN           = 4'd3;
   localparam ST_CPU0_MAIN          = 4'd4;
   localparam ST_CPU1_MAIN          = 4'd5;
   localparam ST_CPU0_MEM           = 4'd6;
   localparam ST_CPU1_MEM       		= 4'd7;
   
   
   //////////////////////////////////////////////////////////////////////////////////
   // Parameters
   //////////////////////////////////////////////////////////////////////////////////
   localparam  LOW =1'b0;
   localparam  HIGH=1'b1;
   
`ifdef SIMULATION
   localparam  T_1S_2M              = 5'd20;
   
`else
   localparam  T_1S_2M              = 24'd2000000;
   
`endif
   
   //////////////////////////////////////////////////////////////////////////////////
   // Internal Signals
   //////////////////////////////////////////////////////////////////////////////////
   reg [3:0]                rstate;
   
   reg                      rStartTimer1s;                                           //Start signal for 1 sec timer (to switch between post codes when more than 1 sequencer sends an error code
   reg                      rClrCntr;                                                //Clear counter signal, to restart the timer (for the post-codes transitions)
   wire                     wTimer1sDone;                                            //Done signal from 1-sec timer (when count reaches 1 sec)
   
   wire                     wSCM_AUX_FAIL;                                           //bit-wise OR with input SCM AUX error code to identify there was a failure in SCM side
   wire                     wCPU_AUX_FAIL;                                           //bit-wise OR with input CPU AUX error code to identify there was a failure in CPU AUX
   wire                     wPSU_MAIN_FAIL;                                          //bit-wise OR with input PSU_MAIN error code to identify there was a failure in PSU_MAIN
   wire                     wCPU0_MAIN_FAIL;                                         //bit-wise OR with input CPU0_MAIN error code to identify there was a failure in CPU0_MAIN
   wire                     wCPU1_MAIN_FAIL;                                         //bit-wise OR with input CPU1_MAIN error code to identify there was a failure in CPU1_MAIN
   wire                     wCPU0_MEM_FAIL;                                          //bit-wise OR with input CPU0_MEM error code to identify there was a failure in CPU0_MEM
   wire                     wCPU1_MEM_FAIL;                                          //bit-wise OR with input CPU1_MEM error code to identify there was a failure in CPU1_MEM
   
   //////////////////////////////////////////////////////////////////////////////////
   // Combinational logic
   //////////////////////////////////////////////////////////////////////////////////
   
   assign      wSCM_AUX_FAIL   = iSCM_PWR_FAULT || iBMC_PWR_FAULT;
   assign      wCPU_AUX_FAIL   = iCPU_AUX_PWR_FLT;
   assign      wPSU_MAIN_FAIL  = (|(iPSU_FLT_CODE)) || iP5V_MAIN_PWR_FAULT;
   assign      wCPU0_MAIN_FAIL = |(iCPU0_FLT_CODE);
   assign      wCPU1_MAIN_FAIL = |(iCPU1_FLT_CODE);
   assign      wCPU0_MEM_FAIL  = |(iCPU0_DIMM_FLT_CODE);
   assign      wCPU1_MEM_FAIL  = |(iCPU1_DIMM_FLT_CODE);
   
   
   //////////////////////////////////////////////////////////////////////////////////
   // Sequencial logic for FSM
   //////////////////////////////////////////////////////////////////////////////////
   always @(posedge iClk or negedge iRst_n) begin
	  if(!iRst_n) begin												                          //synchronous reset condition
		 rstate									<= ST_INIT;
		 
		 rStartTimer1s							<= HIGH;							
		 rClrCntr									<= LOW;
		 
		 oDisplay1								<= 8'hBF;
		 oDisplay2								<= 8'hBF;
	  end
	  
	  else begin
		 case (rstate)
		   ST_INIT: begin
			  rClrCntr							<= LOW;
			  
			  case (iMASTER_POST_CODE)
				4'b0000: begin                                                   //Mstr-Seq in IDLE
				   oDisplay1            <= 8'h40;                                //Display 0.0.
				   oDisplay2            <= 8'h40;
				end
				
				4'b0001: begin                                                   //Mstr-Seq in SCM_AUX
				   oDisplay1            <= 8'h79;                                //Display 0.1.
				   oDisplay2            <= 8'h40;
				   
				end
				
				4'b0010: begin                                                   //Mstr-Seq in CPU_AUX
				   oDisplay1            <= 8'h24;                                //Display 0.2.
				   oDisplay2            <= 8'h40;
				   
				end
				
				4'b0011: begin                                                   //Mstr-Seq in PSU_MAIN
				   oDisplay1            <= 8'h30;                                //Display 0.3.
				   oDisplay2            <= 8'h40;
				   
				end
				
				4'b0100: begin                                                   //Mstr-Seq in CPU_MEM
				   oDisplay1            <= 8'h19;                                //Display 0.4.
				   oDisplay2            <= 8'h40;
				   
				end
				
				4'b0101: begin                                                   //Mstr-Seq in PLTRST
				   oDisplay1            <= 8'h12;                                //Display 0.5.
				   oDisplay2            <= 8'h40;
				   
				end
				
				4'b0110: begin                                                   //Mstr-Seq in PLATFORM_ON
				   oDisplay1            <= 8'h02;                                //Display 0.6.
				   oDisplay2            <= 8'h40;
				   
				end
				
				4'b0111: begin                                                   //Mstr-Seq in ERROR
				   oDisplay1            <= 8'h78;                                //Display 0.7.
				   oDisplay2            <= 8'h40;
				   
				end
				
				4'b1000: begin                                                   //Mstr-Seq in ADR
				   oDisplay1            <= 8'h00;                                //Display 0.8.
				   oDisplay2            <= 8'h40;
				   
				end
				
				4'b1001: begin                                                   //Mstr-Seq in ADR
				   oDisplay1            <= 8'h10;                                //Display 0.9.
				   oDisplay2            <= 8'h40;
				   
				end
				4'b1010: begin                                                   //Mstr-Seq in ADR
				   oDisplay1            <= 8'h08;                                //Display 0.A.
				   oDisplay2            <= 8'h40;
				   
				end
				
				default: begin
				   oDisplay1            <= 8'hFE;                                //Display ..
				   oDisplay2            <= 8'hFE;
				end
			  endcase
			  
			  if(iMASTER_POST_CODE == 4'b0111) begin                              //If Mstr_Seq is in ERROR State, then check Secondary Sequencers for error codes to be displayed instead
				 casex ({wCPU1_MEM_FAIL, wCPU0_MEM_FAIL, wCPU1_MAIN_FAIL, wCPU0_MAIN_FAIL, wPSU_MAIN_FAIL, wCPU_AUX_FAIL, wSCM_AUX_FAIL})
				   7'bxxxxxx1: begin                                             //SCM_AUX Failure
					  rstate            <= ST_SCM_AUX;
					  rStartTimer1s     <= HIGH;
				   end
				   
				   7'bxxxxx10: begin                                             //CPU_AUX Failure
					  rstate            <= ST_CPU_AUX;
					  rStartTimer1s     <= HIGH;
				   end
				   
				   7'bxxxx100: begin                                             //PSU_MAIN Failure
					  rstate            <= ST_PSU_MAIN;
					  rStartTimer1s     <= HIGH;
				   end
				   
				   7'bxxx1000: begin                                             //CPU0_MAIN Failure
					  rstate            <= ST_CPU0_MAIN;
					  rStartTimer1s     <= HIGH;
				   end
				   
				   7'bxx10000: begin                                             //CPU1_MAIN Failure
					  rstate            <= ST_CPU1_MAIN;
					  rStartTimer1s     <= HIGH;
				   end
				   
				   7'bx100000: begin                                             //CPU0_MEM Failure
					  rstate            <= ST_CPU0_MEM;
					  rStartTimer1s     <= HIGH;
				   end
				   
				   7'b1000000: begin                                             //CPU1_MEM Failure
					  rstate            <= ST_CPU1_MEM;
					  rStartTimer1s     <= HIGH;
				   end
				   
				   default: begin                                                //No Failures
					  rstate            <= ST_INIT;
					  rStartTimer1s     <= LOW;
				   end
				 endcase
			  end
		   end
		   
		   ST_SCM_AUX: begin
			  case ({iSCM_PWR_FAULT, iBMC_PWR_FAULT})
				2'b01: begin
				   oDisplay1            <= 8'h79;                                //BMC VR Failure, Display .1.1
				   oDisplay2            <= 8'h79;
				end
				
			    2'b10: begin
				   oDisplay1            <= 8'h24;                                //SCM VR Failure, Display .1.2, reserve .1.3 and .1.4 for SCM_AUX display
				   oDisplay2            <= 8'h79;
				end
				
				default: begin
				   oDisplay1            <= 8'h79;                                //Display .1.1
				   oDisplay2            <= 8'h79;
				end
			  endcase
			  
			  if(wTimer1sDone) begin
				 rClrCntr                <= HIGH;
				 casex ({wCPU1_MEM_FAIL, wCPU0_MEM_FAIL, wCPU1_MAIN_FAIL, wCPU0_MAIN_FAIL, wPSU_MAIN_FAIL, wCPU_AUX_FAIL})
				   6'bxxxxx1: begin                                              //CPU_AUX Failure
					  rstate            <= ST_CPU_AUX;
					  rStartTimer1s     <= HIGH;
				   end
				   
				   6'bxxxx10: begin                                              //PSU_MAIN Failure
					  rstate            <= ST_PSU_MAIN;
					  rStartTimer1s     <= HIGH;
				   end
				   
				   6'bxxx100: begin                                              //CPU0_MAIN Failure
					  rstate            <= ST_CPU0_MAIN;
					  rStartTimer1s     <= HIGH;
				   end
				   
				   6'bxx1000: begin                                              //CPU1_MAIN Failure
					  rstate            <= ST_CPU1_MAIN;
					  rStartTimer1s     <= HIGH;
				   end
				   
				   6'bx10000: begin                                              //CPU0_MEM Failure
					  rstate            <= ST_CPU0_MEM;
					  rStartTimer1s     <= HIGH;
				   end
				   
				   6'b100000: begin                                              //CPU1_MEM Failure
					  rstate            <= ST_CPU1_MEM;
					  rStartTimer1s     <= HIGH;
				   end
				   
				   default: begin                                                //No Failures
					  rstate            <= ST_INIT;
					  rStartTimer1s     <= LOW;
				   end
		         endcase		
			  end
		   end
		   
		   ST_CPU_AUX: begin
			  rClrCntr                   <= LOW;                                  //clear count to restart it   
			  oDisplay1                  <= 8'h12;                                //CPU_AUX VR Failure, Display .1.5, reserve .1.6 and .1.7 for CPU_AUX VR
			  oDisplay2                  <= 8'h79;
			  
			  if(wTimer1sDone && rClrCntr == 1'b0) begin
				 rClrCntr                <= HIGH;
				 casex ({wCPU1_MEM_FAIL, wCPU0_MEM_FAIL, wCPU1_MAIN_FAIL, wCPU0_MAIN_FAIL, wPSU_MAIN_FAIL})
				   5'bxxxx1: begin                                              //PSU_MAIN Failure
					  rstate            <= ST_PSU_MAIN;
					  rStartTimer1s     <= HIGH;
				   end
				   
				   5'bxxx10: begin                                              //CPU0_MAIN Failure
					  rstate            <= ST_CPU0_MAIN;
					  rStartTimer1s     <= HIGH;
				   end
				   
				   5'bxx100: begin                                              //CPU1_MAIN Failure
					  rstate            <= ST_CPU1_MAIN;
					  rStartTimer1s     <= HIGH;
				   end
				   
				   5'bx1000: begin                                              //CPU0_MEM Failure
					  rstate            <= ST_CPU0_MEM;
					  rStartTimer1s     <= HIGH;
				   end
				   
				   5'b10000: begin                                              //CPU1_MEM Failure
					  rstate            <= ST_CPU1_MEM;
					  rStartTimer1s     <= HIGH;
				   end
				   
				   default: begin                                                //No Failures
					  rstate            <= ST_INIT;
					  rStartTimer1s     <= LOW;
				   end
		         endcase		
			  end
		   end
		   
		   ST_PSU_MAIN: begin
			  rClrCntr                   <= LOW;                                  //clear count to restart it
			  case ({iP5V_MAIN_PWR_FAULT, iPSU_FLT_CODE})
				4'b0001: begin                                                   //PS_PWROK Failure
				   oDisplay1                  <= 8'h00;                          //Display .1.8
				   oDisplay2                  <= 8'h79;
				end
				
				4'b0010: begin                                                   //P3V3 VR Failure
				   oDisplay1                  <= 8'h20;                          //Display .1.9
				   oDisplay2                  <= 8'h79;
				end
				
				4'b1000: begin                                                   //P5 VR on SCM Failure
				   oDisplay1                  <= 8'h08;                          //Display .1.A, reserve .1.C and .1.E for PSU_MAIN
				   oDisplay2                  <= 8'h79;
				end
				
				default: begin
				   oDisplay1                  <= 8'h00;                          //Display .1.8
				   oDisplay2                  <= 8'h79;
				end
			  endcase
			  
			  if(wTimer1sDone && rClrCntr == 1'b0) begin
				 rClrCntr                <= HIGH;
				 casex ({wCPU1_MEM_FAIL, wCPU0_MEM_FAIL, wCPU1_MAIN_FAIL, wCPU0_MAIN_FAIL})
				   4'bxxx1: begin                                               //CPU0_MAIN Failure
					  rstate            <= ST_CPU0_MAIN;
					  rStartTimer1s     <= HIGH;
				   end
				   
				   4'bxx10: begin                                               //CPU1_MAIN Failure
					  rstate            <= ST_CPU1_MAIN;
					  rStartTimer1s     <= HIGH;
				   end
				   
				   4'bx100: begin                                               //CPU0_MEM Failure
					  rstate            <= ST_CPU0_MEM;
					  rStartTimer1s     <= HIGH;
				   end
				   
				   4'b1000: begin                                               //CPU1_MEM Failure
					  rstate            <= ST_CPU1_MEM;
					  rStartTimer1s     <= HIGH;
				   end
				   
				   default: begin                                               //No Failures
					  rstate            <= ST_INIT;
					  rStartTimer1s     <= LOW;
				   end
		         endcase		
			  end
		   end
		   
		   ST_CPU0_MAIN: begin
			  rClrCntr                   <= LOW;                                 //clear count to restart it
			  case (iCPU0_FLT_CODE)
				8'b00000001: begin                                              //PVPP_HBM_CPU0
				   oDisplay1                  <= 8'h40;                         //Display .2.0
				   oDisplay2                  <= 8'h24;
				end
				
				8'b00000010: begin                                              //PVCCFA_EHV_CPU0
				   oDisplay1                  <= 8'h24;                         //Display .2.2
				   oDisplay2                  <= 8'h24;
				end
				
				8'b00000100: begin                                              //PVCCFA_EHV_FIVRA_CPU0
				   oDisplay1                  <= 8'h19;                         //Display .2.4
				   oDisplay2                  <= 8'h24;
				end
				
				8'b00001000: begin                                              //PVCCINFAON_CPU0
				   oDisplay1                  <= 8'h02;                         //Display .2.6
				   oDisplay2                  <= 8'h24;
				end
				
				8'b00010000: begin                                              //PVNN_MAIN_CPU0
				   oDisplay1                  <= 8'h00;                         //Display .2.8
				   oDisplay2                  <= 8'h24;
				end
				
				8'b00100000: begin                                              //PVCCD0_HV_CPU0
				   oDisplay1                  <= 8'h08;                         //Display .2.A
				   oDisplay2                  <= 8'h24;
				end
				
				8'b01000000: begin                                              //PVCCIN_CPU_EN0
				   oDisplay1                  <= 8'h46;                         //Display .2.c
				   oDisplay2                  <= 8'h24;
				end
				
				default: begin                                                  
				   oDisplay1                  <= 8'hFF;                         //Display nothing
				   oDisplay2                  <= 8'hFF;
				end
			  endcase
			  
			  if(wTimer1sDone && rClrCntr == 1'b0) begin
				 rClrCntr                <= HIGH;
				 casex ({wCPU1_MEM_FAIL, wCPU0_MEM_FAIL, wCPU1_MAIN_FAIL})							
				   3'bxx1: begin                                                //CPU1_MAIN Failure
					  rstate            <= ST_CPU1_MAIN;
					  rStartTimer1s     <= HIGH;
				   end
				   
				   3'bx10: begin                                                //CPU0_MEM Failure
					  rstate            <= ST_CPU0_MEM;
					  rStartTimer1s     <= HIGH;
				   end
				   
				   3'b100: begin                                                //CPU1_MEM Failure
					  rstate            <= ST_CPU1_MEM;
					  rStartTimer1s     <= HIGH;
				   end
				   
				   default: begin                                               //No Failures
					  rstate            <= ST_INIT;
					  rStartTimer1s     <= LOW;
				   end
		         endcase		
			  end
		   end
		   
		   ST_CPU1_MAIN: begin
			  rClrCntr                   <= LOW;                                 //clear count to restart it
			  case (iCPU1_FLT_CODE)
				8'b00000001: begin                                              //PVPP_HBM_CPU1
				   oDisplay1                  <= 8'h79;                         //Display .2.1
				   oDisplay2                  <= 8'h24;
				end
				
				8'b00000010: begin                                              //PVCCFA_EHV_CPU1
				   oDisplay1                  <= 8'h30;                         //Display .2.3
				   oDisplay2                  <= 8'h24;
				end
				
				8'b00000100: begin                                              //PVCCFA_EHV_FIVRA_CPU1
				   oDisplay1                  <= 8'h12;                         //Display .2.5
				   oDisplay2                  <= 8'h24;
				end
				
				8'b00001000: begin                                              //PVCCINFAON_CPU1
				   oDisplay1                  <= 8'h78;                         //Display .2.7
				   oDisplay2                  <= 8'h24;
				end
				
				8'b00010000: begin                                              //PVNN_MAIN_CPU1
				   oDisplay1                  <= 8'h10;                         //Display .2.9
				   oDisplay2                  <= 8'h24;
				end
				
				8'b00100000: begin                                              //PVCCD0_HV_CPU1
				   oDisplay1                  <= 8'h03;                         //Display .2.b
				   oDisplay2                  <= 8'h24;
				end
				
				8'b01000000: begin                                              //PVCCIN_CPU_EN1
				   oDisplay1                  <= 8'h21;                         //Display .2.d, reserve .2.E and .2.F for CPU_MAIN
				   oDisplay2                  <= 8'h24;
				end
				
				default: begin                                                  
				   oDisplay1                  <= 8'hFF;                         //Display nothing
				   oDisplay2                  <= 8'hFF;
				end
			  endcase
			  
			  if(wTimer1sDone && rClrCntr == 1'b0) begin
				 rClrCntr                <= HIGH;
				 casex ({wCPU1_MEM_FAIL, wCPU0_MEM_FAIL})							
				   2'bx1: begin                                                 //CPU0_MEM Failure
					  rstate            <= ST_CPU0_MEM;
					  rStartTimer1s     <= HIGH;
				   end
				   
				   2'b10: begin                                                 //CPU1_MEM Failure
					  rstate            <= ST_CPU1_MEM;
					  rStartTimer1s     <= HIGH;
				   end
				   
				   default: begin                                               //No Failures
					  rstate            <= ST_INIT;
					  rStartTimer1s     <= LOW;
				   end
		         endcase		
			  end
		   end
		   
		   ST_CPU0_MEM: begin
			  rClrCntr                   <= LOW;                                 //clear count to restart it
			  casex (iCPU0_DIMM_FLT_CODE)
				6'bxxxxx1: begin                                                //DIMM CHANNEL AB Failure
				   oDisplay1                  <= 8'h40;                         //Display .3.0
				   oDisplay2                  <= 8'h30;
				end
				
				6'bxxxx10: begin                                                //DIMM CHANNEL CD Failure
				   oDisplay1                  <= 8'h24;                         //Display .3.2
				   oDisplay2                  <= 8'h30;
				end
				
				6'bxxx100: begin                                                //DIMM CHANNEL EF Failure
				   oDisplay1                  <= 8'h19;                         //Display .3.4
				   oDisplay2                  <= 8'h30;
				end
				
				6'bxx1000: begin                                                //DIMM CHANNEL GH Failure
				   oDisplay1                  <= 8'h02;                         //Display .3.6
				   oDisplay2                  <= 8'h30;
				end
				
				6'bx10000: begin                                                //DIMM CHANNEL IJ Failure
				   oDisplay1                  <= 8'h00;                         //Display .3.8
				   oDisplay2                  <= 8'h30;
				end
				
				6'b100000: begin                                                //DIMM CHANNEL KL Failure
				   oDisplay1                  <= 8'h08;                         //Display .3.A
				   oDisplay2                  <= 8'h30;
				end
				
				default: begin                                                  
				   oDisplay1                  <= 8'hFF;                         //Display nothing
				   oDisplay2                  <= 8'hFF;
				end
			  endcase
			  
			  if(wTimer1sDone && rClrCntr == 1'b0) begin
				 rClrCntr                <= HIGH;
				 casex (wCPU1_MEM_FAIL)														
				   1'b1: begin                                                 //CPU1_MEM Failure
					  rstate            <= ST_CPU1_MEM;
					  rStartTimer1s     <= HIGH;
				   end
				   
				   default: begin                                               //No Failures
					  rstate            <= ST_INIT;
					  rStartTimer1s     <= LOW;
				   end
		         endcase		
			  end
		   end
		   
		   ST_CPU1_MEM: begin
			  rClrCntr                   <= LOW;                                 //clear count to restart it
			  casex (iCPU1_DIMM_FLT_CODE)
				6'bxxxxx1: begin                                                //DIMM CHANNEL AB Failure
				   oDisplay1                  <= 8'h79;                         //Display .3.1
				   oDisplay2                  <= 8'h30;
				end
				
				6'bxxxx10: begin                                                //DIMM CHANNEL CD Failure
				   oDisplay1                  <= 8'h30;                         //Display .3.3
				   oDisplay2                  <= 8'h30;
				end
				
				6'bxxx100: begin                                                //DIMM CHANNEL EF Failure
				   oDisplay1                  <= 8'h12;                         //Display .3.5
				   oDisplay2                  <= 8'h30;
				end
				
				6'bxx1000: begin                                                //DIMM CHANNEL GH Failure
				   oDisplay1                  <= 8'h78;                         //Display .3.7
				   oDisplay2                  <= 8'h30;
				end
				
				6'bx10000: begin                                                //DIMM CHANNEL IJ Failure
				   oDisplay1                  <= 8'h10;                         //Display .3.9
				   oDisplay2                  <= 8'h30;
				end
				
				6'b100000: begin                                                //DIMM CHANNEL KL Failure
				   oDisplay1                  <= 8'h03;                         //Display .3.b
				   oDisplay2                  <= 8'h30;
				end
				
				default: begin                                                  
				   oDisplay1                  <= 8'hFF;                         //Display nothing
				   oDisplay2                  <= 8'hFF;
				end
			  endcase
			  
			  if(wTimer1sDone && rClrCntr == 1'b0) begin
				 rClrCntr                <= HIGH;                                
				 rstate                  <= ST_INIT;                            //ST_INIT
				 rStartTimer1s           <= LOW;		
			  end
		   end
		   
		   default: begin
			  rClrCntr							<= LOW;
			  rstate                     <= ST_INIT;                            //ST_INIT
			  rStartTimer1s              <= LOW;
		   end
		 endcase
	  end
   end
   
   
   
   //////////////////////////////////////////////////////////////////////////////////
   // Instance
   //////////////////////////////////////////////////////////////////////////////////
   
   delay #(.COUNT(T_1S_2M)) 
   Timer1sec(
             .iClk(iClk),                            //2MHz clock signal
             .iRst(iRst_n),
             .iStart(rStartTimer1s),
             .iClrCnt(rClrCntr),                     //clears the count regardless of Start signal
             .oDone(wTimer1sDone)
             );
   
   
endmodule
